For the production of structures in the nanometer range, optical lithography, among others, is used. In that case, with the aid of masking techniques, exposure is employed to transfer the desired structure to a photosensitive lacquer. The latter then serves as the mask for producing the ultimate structure. This conventional optical lithography enables a resolution of up to about 130 nanometers to be obtained. Methods with still better resolution, like x-ray lithography, electron beam lithography or deep-uv lithography are already known at a laboratory scale and require extensive technological efforts at high cost ®. (Kassing, R. Käsmeier, I. W. Rangelow, Physikalische Blätter, Vol. 56, 2000).
In microelectronics, the production of structures with dimensions of less than 100 nm is highly desirable. In semiconductor technology, such structures provide the basis for producing the smallest electronic components, for example, silicon MOSFETS. The extremely rapid advance of miniaturization of such components has required increasing development of chip technology. In the field of silicon technology, the requirements of future developments in components and the requisite dimensions of structuring have been given in “International Technology Roadmap for Semiconductors, Semiconductor Industry Association (http://public.itrs.net)”.
The production of nanostructures and thus structures smaller than 100 nm plays an important role not only in microelectronics but is also a key step in nanotechnology generally. Here there is a great need for alternative fabrication techniques to eliminate the extreme costs and requirements of lithographic processes and to generate structures even within present day resolution limits.
Aside from the problem of producing the smallest structures in photolacquers, the problem of transfer of these structures to the underlying layers, usually achieved with etching processes have become increasingly problematical with decreasing dimensions, especially when one operates in the nanometer range since here the dimensions amount to only several atomic diameters.
In the case of silicon technology, among the materials used, silicides have been found to play a special role with respect to their electrical properties. They are used, for example, as contact materials and conducting materials in highly integrated circuits. A silicide of the greatest importance in microelectronics has been cobalt disilicide. The structuring of cobalt disilicide has been problematical or difficult in the past since, for that purpose, no standardized etching process exists. This is especially notable for the structuring of layers in the range smaller than 100 nm.
Methods which rely upon self-adjusting processes have been provided an alternative to structuring by means of lithography. From DE 195 03 641 A1, a method for structuring of silicide layers has become known which relies upon the local oxidation of silicides. With a self-adjusting process, for example, a cobalt disilicide layer can be divided into two regions.
A method of nanostructuring which relies upon a self-adjusting process is known from DE 198 53 023 A1. The method involves the formation of a submicrometer structured layer on a substrate whereby one layer is initially formed on a substrate. The means for creating elastic strain on at least one predetermined process of this layer is applied and then the layer is subjected to a solid body reaction which is a function of the strain. This gives rise to a separation of material and subsequently to a structuring of the layer at its position. The structure, depending upon the starting layer sequence, can have structure edges with a spacing of at least 30 to 50 nm. Smaller structures cannot be made in this way.
These structuring methods are disadvantageous because of their process-determined resolution limits. A change, especially a further reduction of the structure sizes produced by the method is not possible within these processes.